monolithic cmos analog multiplexers dg506a/dg507a 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim?s website at www.maxim-ic.com. general description maxim?s dg506a/dg507a are monolithic cmos analog multiplexers. the dg506a is a single 16-channel (1 of 16) multiplexer and the dg507a is a differential 8-chan - nel (2 of 16) multiplexer. both devices feature break-before-make switching. maxim guarantees that these multiplexers will not latch- up if the power supplies are turned off with the input signals still present as long as absolute maximum ratings are not violated. the multiplexers operate over a wide range of power supplies from q 4.5v to q 18v. compared to the original manufacturer?s devices, maxim?s dg506a/dg507a consume significantly less power, making them ideal for portable equipment. maxim?s dg506a/dg507a meet or exceed the speci - fications of, and are drop-in replacements for intersil?s ih6116 and ih6216, siliconix?s dg506a and dg507a, and harris? hi506 and hi507. applications control systemsdata logging systems aircraft heads up displays data acquisition systems signal routing features s improved 2nd source s pin compatible with harris, siliconix, intersil s operable with 4.5v to 18v supplies s symmetrical, bidirectional operation s logic and enable inputs, ttl and cmos compatible s latch-up proof construction s monolithic, low-power cmos design 19-0482; rev 4; 6/12 pin configurations ordering information ? devices are available in a lead(pb)-free/rohs-compliant package, specify lead-free by adding ?+? to the part number when ordering. pin configurations continued in middle of data sheet. clock in q b q c q a a h1 b h1 nc +15v +15v v + gnd r 02 r 01 q d nc analog input (outputs) -15v -15v analogoutput (inputs) enable in (mux on-off control) a 0 a 1 a 2 gnd en v + v - d a d b s 1b s 8b s 1a s 8a dg507a 8-channel sequential differential mux/demux 2827 26 25 24 23 22 21 20 19 18 17 16 15 12 3 4 5 6 7 8 9 1011 12 13 14 dv - s 8 s 7 s 6 s 5 a 2 s 4 s 3 s 2 s 1 ena 0 a 1 a3 nc gnd s 9 s 10 s 11 s 12 s 13 s 14 s 15 s 16 nc nc v + 2827 26 25 24 23 22 21 20 19 18 17 16 15 12 3 4 5 6 7 8 9 1011 12 13 14 d a v - s 8a s 7a s 6a s 5a a 2 s 4a s 3a s 2a s 1a ena 0 a 1 nc wide so/dip wide so/dip nc gnd s 1b s 2b s 3b s 4b s 5b s 6b s 7b s 8b nc d b v + dg506a dg507a part ? temp range pin-package dg506 aak -55c to +125c 28 cerdip dg506abk -25c to +85c 28 cerdip dg506ac/d 0c to +70c dice dg506acj 0c to +70c 28 plastic dip dg506ack 0c to +70c 28 cerdip dg506acwi 0c to +70c 28 wide so dg506amwi/pr -55c to +125c 28 wide so dg506aaz/833b -55c to +125c 28 lcc dg507 aak -55c to +125c 28 cerdip dg507abk -25c to +85c 28 cerdip dg507ac/d 0c to +70c dice dg507acj 0c to +70c 28 plastic dip dg507ack 0c to +70c 28 cerdip dg507acwi 0c to +70c 28 wide so downloaded from: http:/// typical operating circuit
monolithic cmos analog multiplexers dg506a/dg507a 2 stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (voltages referenced to v - .) v + .......................................................................................... 44v gnd ....................................................................................... 25v digital inputs v s , v d (note 1) ....................... -2v to (v + + 2v) or 20ma, whichever occurs first current, any terminal except s or d ................................. 30ma continuous current, s or d ................................................ 20ma peak current, s or d (pulsed at 1ms, 10% duty cycle max) ... 40ma continuous power dissipation (t a = +70c)* 28-pin ceramic dip (derate 16.7mw/ n c above +70 n c) . 1333mw 28-pin plastic dip (derate 14.3mw/ n c above +70 n c) .. 1143mw 28-pin wide so (derate 12.5mw/c above +70c) . 1000mw 28-pin lcc (derate 10.2mw/c above +70c) ....... 816.3mw operating temperature range (a suffix) ........ -55 n c to +125 n c (b suffix) .......... -25 n c to +85 n c (c suffix) ................ 0 n c to +70 n storage temperature (a and b suffix) ............. -65 n c to +150 n c (c suffix) ....................... -65 n c to +125 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) lead (pb)-free packages ............................................ +260 n c packages containing lead (pb) ................................... +240 n c electrical characteristics (v+ = 15v, v- = -15v, v gnd = 0v, t a = +25 n c, unless otherwise indicated.) absolute maximum ratings * all leads soldered or welded to pcb. parameter symbol conditions dg506aadg507aa dg506ab/cdg507ab/c units min (note 2) typ (note 3) max min (note 2) typ (note 3) max switchanalog signal range v analog -15 +15 -15 +15 v drain-to-source on-resistance r ds(on) sequence each switch on, v al = 0.8v, v ah = 2.4v, v en = 2.4v v d = 10v, i s = -200 f a 270 400 270 450 i v d = -10v, i s = -200 f a 230 400 230 450 greatest change in drain-source on-resistance between channels r ds(on) ds(on)max ds(on)min ds(on) ds(on)ave rr r r ?? ? ?= ?? ?? ?? -10v p v s p +10v 6 6 % source off-leakage current i s(off) v en = 0.8v, v al = 0.8v v s = 10v, v d = -10v -1 0.002 +1 -5 0.002 +5 na v s = -10v, v d = 10v -1 -0.005 +1 -5 -0.005 +5 drain off-leakage current i d(off) dg506a, v en = 0.8v, v al = 0.8v v d = 10v, v s = -10v -10 0.02 +10 -20 0.02 +20 na v d = -10v, v s = 10v -10 -0.03 +10 -20 -0.03 +20 dg507a, v en = 0.8v, v al = 0.8v v d = 10v, v s = -10v -5 0.007 +5 -10 0.007 +10 v d = -10v, v s = 10v -5 -0.015 +5 -10 -0.015 +10 downloaded from: http:///
monolithic cmos analog multiplexers dg506a/dg507a 3 electrical characteristics (continued) (v+ = 15v, v- = -15v, v gnd = 0v, t a = +25 n c, unless otherwise indicated.) parameter symbol conditions dg506aadg507aa dg506ab/cdg507ab/c units min (note 2) typ (note 3) max min (note 2) typ (note 3) max channel on-leakage current i d(on) (note 4) dg506a, sequence each switch on, v al = 0.8v, v ah = 2.4v, v en = 2.4v v s(all) = v d = 10v -10 0.03 +10 -20 0.03 +20 na v s(all) = v d = -10v -10 -0.06 +10 -20 -0.06 +20 dg507a, sequence each switch on, v al = 0.8v, v ah = 2.4v, v en = 2.4v v s(all) = v d = 10v -5 0.015 +5 -10 0.015 +10 v s(all) = v d = -10v -5 -0.03 +5 -10 -0.03 +10 inputaddress input current, input- voltage high i ah v a = 2.4v -10 -0.002 -10 -0.002 f a v a = 15v 0.006 10 0.006 10 address input current, input- voltage low i al all v a = 0v v en = 2.4v -10 -0.002 -10 -0.002 f a v en = 0v -10 -0.002 -10 -0.002 dynamicswitching time of multiplexer t transition figure 1 0.6 1 0.06 f s break-before-make interval t open figure 3 0.2 0.2 f s enable turn-on time t on(en) figure 2 1 1 f s enable turn-off time t off(en) figure 2 0.4 0.4 f s off-isolation (note 5) oirr v en = 0v, r l = 1k i , c l = 15pf, v s = 7v rms , f = 500khz 68 68 db source off-capacitance c s(off) v en = 0v, f = 140khz, v s = 0v 6 6 pf drain off-capacitance c d(off) v en = 0v, f = 140khz dg506a, v d = 0v 45 45 pf dg507a, v d = 0v 23 23 supplypositive supply current i + v en = 0 or 5v, all v a = 0v 0.13 0.25 0.13 0.3 ma negative supply current i - v en = 0 or 5v, all v a = 0v -0.15 -0.07 -0.25 -0.07 downloaded from: http:///
monolithic cmos analog multiplexers dg506a/dg507a 4 electrical characteristics ( overtemperature) (v+ = 15v, v- = -15v, v gnd = 0v, t a = overtemperature range, unless otherwise noted .) parameter symbol conditions dg506aadg507aa dg506ab/cdg507ab/c units min (note 2) typ (note 3) max min (note 2) typ (note 3) max switchanalog signal range v analog -15 +15 -15 +15 v drain-to-source on-resistance r ds(on) sequence each switch on, v al = 0.8v, v ah = 2.4v, v en = 2.4v v d = 10v, i s = -200 f a 500 550 i v d = -10v, i s = -200 f a 500 550 source off-leakage current i s(off) v en = 0.8v, v al = 0.8v v s = 10v, v d = -10v -50 +50 -50 +50 na v s = -10v, v d = 10v -50 +50 -50 +50 drain off-leakage current i d(off) dg506a, v en = 0.8v, v al = 0.8v v d = 10v, v s = -10v -300 +300 -300 +300 na v d = -10v, v s = 10v -300 +300 -300 +300 dg507a, v en = 0.8v, v al = 0.8v v d = 10v, v s = -10v -200 +200 -200 +200 v d = -10v, v s = 10v -200 +200 -200 +200 channel on-leakage current i d(on) (note 4) dg506a, sequence each switch on, v al = 0.8v, v an = 2.4v, v en = 2.4v v s(all) = v d = 10v -300 +300 -300 +300 na v s(all) = v d = -10v -300 +300 -300 +300 dg507a, sequence each switch on, v al = 0.8v, v an = 2.4v, v en = 2.4v v s(all) = v d = 10v -200 +200 -200 +200 v s(all) = v d = -10v -200 +200 -200 +200 inputaddress input current, input- voltage high i ah v a = 2.4v -30 -30 f a v a = 15v 30 30 address input current, input- voltage low i al all v a = 0v v en = 2.4v -30 -30 f a v en = 0v 30 30 downloaded from: http:///
monolithic cmos analog multiplexers dg506a/dg507a 5 electrical characteristics ( overtemperature ) ( continued) (v+ = 15v, v- = -15v, v gnd = 0v, t a = over temperature range, unless otherwise noted.) note 1: signals on s x , d x , or in x exceeding v+ or v- will be clamped by internal diodes. limit forward diode current to maximum current ratings. note 2: the algebraic convention whereby the most negative value is a minimum, and the most positive value is a maximum, is used in this data sheet. note 3: typical values are for design aid only, not guaranteed nor subject to production testing. note 4: i d(on) is leakage from driver into on switch. note 5: off-isolation = 20log x v o /v s , v s = input to off switch, v d = output due to v s . truth tables switching time test circuits figure 1a. transition switching time figure 1b. transition switching time note: logic ?0? = v al 0.8v, logic ?1? = v ah 2.4v, ?0? = don?t care. +2.4v 10v s 1 10v s 16 a 1 a 2 a 0 en a 3 +15v v + v - -15v dg506a gnd switchoutput v o 1m ? d 50 ? logic input s 2 thru s 15 35pf +2.4v 10v s 1b 10v s 8b a 1 a 2 a 0 en +15v v + v - -15v dg507a gnd switch output v o 1m ? d b 50 ? logic input s 2b, and s 7b s 1a thru s 8a, d a 35pf a3 a2 a1 a0 en on switch x x x x 0 none 0 0 0 0 1 1 0 0 0 1 1 2 0 0 1 0 1 3 0 0 1 1 1 4 0 1 0 0 1 5 0 1 0 1 1 6 0 1 1 0 1 7 0 1 1 1 1 8 1 0 0 0 1 9 1 0 0 1 1 10 1 0 1 0 1 11 1 0 1 1 1 12 1 1 0 0 1 13 1 1 0 1 1 14 1 1 1 0 1 15 1 1 1 1 1 16 a2 a1 a0 en on switch x x x 0 none 0 0 0 1 1 0 0 1 1 2 0 1 0 1 3 0 1 1 1 4 1 0 0 1 5 1 0 1 1 6 1 1 0 1 7 1 1 1 1 8 downloaded from: http:///
monolithic cmos analog multiplexers dg506a/dg507a 6 switching time test circuits (continued) figure 2a. enable switching timefigure 2b. enable switching time figure 3. break-before-make figure 4. timing diagrams for figures 1, 2, and 3 -5v s 1 a 1 a 2 a 0 en a 3 +15v v + v - -15v dg506a gnd switchoutput v o 1k ? d 50 ? logic input s 2 thru s 16 35pf -5v s 1b a 1 a 2 a 0 en +15v v + v - -15v dg507a gnd switchoutput v o 1k ? 35pf d b 50 ? logic input s 1a thru s 4a, d a, s 2b, s 3b, s 4b +2.4v v s = +5v all s and d a a 0 a 1 a 2 a 3 en +15v v + v - -15v dg506adg507a gnd switchoutput v o 1k ? d b, d 50 ? logic input 35pf logic inputt r < 20ns t i < 20ns switch output v o (see figure 1) transition time switch output v o (see figure 2) enable t (on) t (off) time switch output v o (see figure ) v 0 0 t on (en) 01 v o 0 0 v o v o v s v s 0 0v s on t (en) v s1 0 v s1 0 v s v s t trnsitin s1 on t trnsitin 0 open timebreabeforemae interval t open downloaded from: http:///
monolithic cmos analog multiplexers dg506a/dg507a 7 pin description pin configurations (continued) in15in14 in13 in12 in11 in10 in9 in7in6 in5 in4 in3 in2 in1 in16n.c. n.c. v+ out v- in8 gnd n.c. a3a2 a1 a0 en lcc 12 13 14 15 16 17 18 1234 26 27 28 19 20 21 22 23 24 25 56 7 8 9 10 11 dg506a n.c. = no internal connection pin name function dg506a dip / so dg507a dip / so 1 1 v+ positive supply voltage input 2, 3 3 n.c. no connection. internally not connected. ? 2 d b analog output bidirectional channel b 4 ? s 16 analog output bidirectional channel 16 ? 4 s 8b analog output bidirectional channel 8b 5 ? s 15 analog output bidirectional channel 15 ? 5 s 7b analog output bidirectional channel 7b 6 ? s 14 analog output bidirectional channel 14 ? 6 s 6b analog output bidirectional channel 6b 7 ? s 13 analog output bidirectional channel 13 ? 7 s 5b analog output bidirectional channel 5b 8 ? s 12 analog output bidirectional channel 12 ? 8 s 4b analog output bidirectional channel 4b 9 ? s 11 analog output bidirectional channel 11 ? 9 s 3b analog output bidirectional channel 3b 10 ? s 10 analog output bidirectional channel 10 ? 10 s 2b analog output bidirectional channel 2b 11 ? s 9 analog output bidirectional channel 9 ? 11 s 1b analog output bidirectional channel 1b 12 12 gnd ground downloaded from: http:///
monolithic cmos analog multiplexers dg506a/dg507a 8 pin description (continued) pin name function dg506a dip / so dg507a dip / so 13 13, 14 n.c. no connection. not internally connected. 14 ? a3 address input a3 15 15 a2 address input a2 16 16 a1 address input a1 17 17 a0 address input a0 18 18 en enable input 19 ? s 1 analog output bidirectional channel 1 ? 19 s 1a analog output bidirectional channel 1a 20 ? s 2 analog output bidirectional channel 2 ? 20 s 2a analog output bidirectional channel 2a 21 ? s 3 analog output bidirectional channel 3 ? 21 s 3a analog output bidirectional channel 3a 22 ? s 4 analog output bidirectional channel 4 ? 22 s 4a analog output bidirectional channel 5 23 ? s 5 analog output bidirectional channel 5a ? 23 s 5a analog output bidirectional channel 6 24 ? s 6 analog output bidirectional channel 6a ? 24 s 6a analog output bidirectional channel 7 25 ? s 7 analog output bidirectional channel 7a ? 25 s 7a analog output bidirectional channel 8 26 ? s 8 analog output bidirectional channel 8a ? 26 s 8a analog output bidirectional channel 27 27 v- negative supply voltage input 28 ? d analog output bidirectional ? 28 da analog output bidirectional channel a downloaded from: http:///
monolithic cmos analog multiplexers dg506a/dg507a 9 pin description (continued) package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a ?+?, ?#?, or ?-? in the package code indicates rohs status only. package drawings may show a different suffix number, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 28 cerdip j28-2 21-0046 ? 28 plastic dip p28-2 21-0044 ? 28 wide so w28-5 21-0042 90-0109 28 wide so w28-5 21-0047 90-0178 28 lcc l28-2 21-4497 90-0178 pin name function dg506a lcc 1 v+ positive supply voltage input 2, 3 n.c. noconnection. internally not connected. 4 in 16 analog input bidirectional channel 16 5 in 15 analog input bidirectional channel 15 6 in 14 analog input bidirectional channel 14 7 in 13 analog input bidirectional channel 13 8 in 12 analog input bidirectional channel 12 9 in 11 analog input bidirectional channel 11 10 in 10 analog input bidirectional channel 10 11 in 9 analog input bidirectional channel 9 12 gnd ground 13 n.c. no connection. not internally connected. 14 a3 address input a3 15 a2 address input a2 16 a1 address input a1 17 a0 address input a0 18 en enable input 19 in 1 analog input bidirectional channel 1 20 in 2 analog input bidirectional channel 2 21 in 3 analog input bidirectional channel 3 22 in 4 analog input bidirectional channel 4 23 in 5 analog input bidirectional channel 5 24 in 6 analog input bidirectional channel 6 25 in 7 analog input bidirectional channel 7 26 in 8 analog input bidirectional channel 8 27 v- negative supply voltage input 28 out analog output bidirectional downloaded from: http:///
monolithic cmos analog multiplexers dg506a/dg507a maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. 10 maxim integrated products, inc. 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 ? 2012 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 8/92 initial release ? 1 1/99 updated to word format. 1?7 2 5/09 added ruggedized plastic part. 1?4, 7 3 2/10 ? added lead temperature to the absolute maximum ratings . ? changed the derate rate of all packages to above 70c in the absolute maximum ratings . 2 4 6/12 added dg506aaz/883b; added the pin descriptions for dg506a dip/so, dg507a dip/so, dg506a lcc; added lcc pin configuration for the dg506a 1, 2, 7, 9 downloaded from: http:///
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